1. Field of the Invention
The present invention relates to a peripheral circuit of a scan chain and particularly to a circuit for control and observation of a scan chain.
2. Description of the Prior Art
FIG. 1 is a diagram showing a conventional scan chain. It includes five (for example) shift registers 11˜15 connected in series. Each of the shift registers 11˜15 is a scan cell. The first shift register 11 receives a data signal from a tester (not shown). In response to a clock signal, the bits carried by the data signal are forwarded through the shift registers 11˜15 one by one and stored therein. Then, the stored bits are sent to a device under test (DUT). The data with which the DUT responds to the scan chain is sent back to the tester for data comparison. Results of the data comparison determine whether the DUT fails.
The results of the data comparison are reliable only when the scan chain operates correctly. If any one of the shift register 11˜15 malfunctions so that its output gets stuck at “1”, the final output of the scan chain will also get stuck at “1” despite any “0” bit in the data signal. However, in the conventional scan chain, there is no means for monitoring the scan cells.